Co-pending and commonly-assigned U.S. patent application Ser. No. 11/183,198, file on Jul. 15, 2005, by Poplevine et al. titled “Non-volatile Memory Cell with Improved Programming Technique” and which is the subject of a Notice of Allowance issued by the U.S. Patent Office on Nov. 2, 2006, discloses a 4-transistor PMOS non-volatile memory (NVM) cell that includes an embedded static random access memory (SRAM) cell. The NVM cell utilizes a reverse Fowler-Nordheim tunneling programming technique with a very low programming current that allows an entire NVM cell array to be programmed at a single cycle. Application Ser. No. 11/183,198 is incorporated herein by reference to provide background information regarding the present invention.
Co-pending and commonly-assigned U.S. patent application Ser. No. 11/182,115, filed on Jul. 15, 2005, by Poplevine et al., titled “Reverse Fowler-Nordheim Tunneling Programming for Non-volatile Memory Cell,” discloses a low current programming method for a non-volatile memory (NVM) cell utilizing reverse Fowler-Nordheim tunneling. Application Ser. No. 11/182,115 is incorporated herein by reference to provide background information regarding the present invention.
Co-pending and commonly-assigned U.S. patent application Ser. No. 11/235,834, filed on Sep. 26, 2005, by Poplevine et al., titled “Method of Hot Electron Injection Programming of a Non-volatile Memory (NVM) Cell Array in a Single Cycle,” discloses a 4-transistor non-volatile memory (NVM) cell that includes a static random access memory (SRAM) cell. The cell utilizes a hot electron injection programming technique which, in combination with the SRAM cell and a sequence of cascaded pass gates, allows an entire NVM cell array, or a selected row or sector of the array, to be programmed at a single cycle. Application Ser. No. 11/235,834 is incorporated herein by reference to provide background information regarding the present invention.